Minimizing and Exploiting Leakage in VLSI Design

This Book focuses on minimizing leakage power consumption in VLSI design. The authors examine leakage currents and their impact on circuit performance, especially in the context of scaling down transistors. They introduce novel design methodologies such as the High-Leakage (HL) approach and a combined input vector control and circuit modification technique, aiming to reduce leakage without compromising speed. They also explore adaptive body biasing as a means to compensate for process, voltage, and temperature (PVT) variations. The paper concludes with the design and fabrication of a sub-threshold BFSK transmitter chip, showcasing the practical application of these leakage reduction techniques and demonstrating the potential for power-efficient circuits.

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