An Interview with Claire (née 'Clifford') Wolf

Claire, formerly Clifford, took on a new name in December 2019. We decided to update the post.

Welcome, Claire Wolf (Twitter: @OE1CXW)

• Claire's first open source project was RockLinux, started back in 1997
  • Shell scripts, AWK scripts
  • A fork of the project still is active as T2
• OpenSCAD is an open source scripted 3D CAD program
  • Metalab.at hackerspace
  • Creating parametric models that can be modified easily in OpenSCAD.
• FPGAs
  • Claire started out with Xilinx because they offered HDL as the default.
  • She did things like building CPUs, writing compilers and creating the SPL scripting language
  • The Dragon book was her intro to writing a compiler
• 3D laser scanners / LIDAR
  • Light is too fast
  • Light is too slow
  • Self driving cars will likely move to cameras in the future because of interference of multiple LIDAR systems on the road.
• In 2008 she went back to university
  • Her academics were overshadowed by focusing on missing questions here and there. So instead she focused on publishing papers
  • Coarse-Grain Reconfigurable Architectures
    • "Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures. Johann Glaser and Clifford Wolf. In Jan Haase, editor, Models, Methods, and Tools for Complex Chip Design. Lecture Notes in Electrical Engineering. Volume 265, 2014, pp 201-221. Springer, 2013."
• Yosys
  • A framework for HDL synthesis and more
  • Verilog 2005
  • Reinforcement learning
  • Logic Synthesis - turning verilog into a logic circuit
  • Intocent
  • File formats for logic circuits
    • edif
    • blif
    • verilog
    • json
• Project IceStorm
  • iCE40 from Lattice
  • Documented the bitstream format
  • mid-2015, complete open source toolchain
  • Later added 8K, then ultra plus device

• arachne-pnr - written by Cotton Seed
• "Whenever you have a theory write a small program that checks if your theory is correct"
• New versions will target Xilinx 7 parts
  • Partial reconfiguration will allow an "FPGA within the FPGA, where the harness is made in vendor tools
  • "Prototyping tools in ARM processor"
  • Example: Logic analyzer trigger conditions
• RISC V
  • This is an open instruction set architecture (ISA) -- not open source
  • Western Digital will be shipping 1B RISC V devices in 2019.
  • The software tools is the hard part
  • XKCD standards
  • ARM put m0 and m3 on webpage

• PicoRV32
  • This was part of the subject of Claire's CCC talk this year.
  • It's a fast, small processor, which reduces clock domain crossing
  • It's used in the Berkeley Lawrence Nat'l lab synchrotron
• Libxsvf
  • Used in one of the control coils for the Large Hadron Collider
  • Has the LHC Destroyed the world yet?
• RISC V vs x86 is a red herring
• Formal Verification
  • This is the goal for Claire's company, SymbioticEDA.com
  • The idea is to do hardware model checking and "prune the search tree as soon as possible"
  • SAT/SMT solving
  • SymbiYosis
  • Yosys-SMTBMC
  • Project IceStorm uses formal verification
• riscv-formal
  • Formally verify a processor against ISA
  • This is actually what the latest CCC (34c3) talk was, End to End ISA Verification of a RISC V processor.
  • Reactive synthesis (starting from random and seeing if it's a processor)
  • Instead this is starting from a processor and running "all programs" against it
  • Category of bugs:
    • Reading spec incorrectly
    • Function is different from what it usually does in one specific application
  • New intel bug